Direct Digital Synthesis (DDS) is an electronic method of generating the arbitrary waveforms and frequencies from a single, fixed frequency source. DDS has two major components namely Phase Accumulator (PA), which linearly increases the given phase value for every clock cycle and Phase-to-Amplitude converter (PAC), generates the amplitude of a waveform from phase value at every clock cycle. This paper presents a DDS design in which the Phase Accumulator is constructed using the Kogge Stone adder (KSA) a faster parallel prefix form of Carry Look-Ahead adder. It generates the carry signal with the delay of log2 N time, using reversible logic. The reversible circuits generate the unique outputs from specified inputs and vice versa and so, there is no loss of bits during logic computation resulting in reduction of power dissipation and propogation delay of the circuits. The better performance of this DDS design is compared with existing DDS architecture containing Phase Accumulator built using non reversible Carry Look-Ahead adder. In both existing and proposed designs pipelined CORDIC Algorithm is used for Phase-to-Amplitude conversion. The proposed DDS design has a reduction in the delay by 24% compared to the existing DDS design, when synthesized in Xilinx Vivado 2017.2 by taking the Zed Board as target device.
Volume 11 | 03-Special Issue
Pages: 1651-1659