Low Power Silicon-On-Insulator Heterojunction Tunneling Transistor Architectures Analysis at Device Level

B.V.V. Satyanarayana and M. Durga Prakash

An era of accelerated technological progress characterized by innovations whose rapid application caused abrupt changes in the electronics industry for the past eight decades. Due to these advancements in the technology, there is a solemn drift towards the portable electronic systems in human life. These systems consist of adders, multiplexers, registers, memories. The major stumbling block of these portable mobile systems is the amount of power consumption. Memories are more power consuming components in embedded applications. To avoid the frequent charging of the batteries embedded systems should be equipped with large battery sources. The capacity of the battery depends on the power consumption of the system. The higher the power consumption, the higher is the battery capacity which is unacceptable for portable embedded systems. So, for better performance of integrated systems, we need effective low power VLSI techniques. Many authors proposed low power techniques for design and implementation of the systems, but the low voltage operation is the most effective energy saving method. Low power and ultra-low power applications for different heterojunction tunneling architectures have been analyzed and presented in this paper. Analysis of heterojunction architectures can be done with ION / IOFF ratio, leakage current, subthreshold swing (SS) and materials used for manufacturing and the trade-off between these parameters is required. Therefore, the proposed architecture addresses high ION / IOFF ratio, steeper subthreshold swing and improved Miller capacitance with less leakage current. These structures thereby enhance the performance of the heterojunction architectures.

Volume 11 | 04-Special Issue

Pages: 1976-1982