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Investigation on One Bit Full Adder Architecture Using T-Spice


Dr.P. Sukumar, G. Prabhakaran, E.K. Arul Karthick, Amarnathprabhakaran
Abstract

A full adder is one of the essential component in digital circuit design, many improvements have been made to reduce the architecture of a full adder. The main aim of this paper is to reduce the power dissipation and improve output swing by 4-T transistor the number of transistors. By using general logic of CMOS transistor, the four transistor XOR gate can be implemented. In this paper proposes the novel design of a 4-T XOR gate. The design has been compared with earlier proposed 4T and 4-T XOR gate and a significant improvement in power and output swing level has been obtained. A 14-T full adder has been designed using the proposed 4-T XOR gate and its performance has been obtained. The design is simulated by using Tanner.

Volume 11 | Issue 4

Pages: 67-74