The presence of memory elements is in the rise in digital systems. The need for faster memory elements like latches and flip-flops are increasing day by day. The proposed flip-flop provides ratio less design and faster rise operation. In this project a new sense-amplifier based flip-flop (SAFF) with a differential dynamic structure for its sampling is proposed for high-performance and low power application. For low supply voltage (VDD) operation, a high speed and highly reliable sense amplifier based flip-flop has been proposed. The Sense amplifier based flip- flop adopts the internally generated detection signal to indicate the completion of sense-amplifier stage transition. The operational yield degradation, current contention, and glitches of previous SAFFs can be further upgraded by the detection signal gates to the pull-down path of the sense-amplifier stage and the slave latch. The Proposed and previous flip-flops are operational yield, speed, hold time, energy consumption and area.
Volume 11 | 04-Special Issue
Pages: 1229-1235