Design and Implementation of Fundamental Calculation Method by Using Cordic Algorithm

A.R. Santhosh, K. Saranya and T. Prema Kumari

The implementation of low complexity digital multiplier by using the CORDIC algorithm well known interactive algorithm for performing a rotation in VLSI design. Then the primary objective of CORDIC increase the clock speed and reduce the critical path delay. The model of a power and area efficient high-speed bit multiplier based on Fast Fourier Transform (FFT) multiplication for CORDIC processes. The technique is enabling computation to the performed directly on encrypted data, thereby preserving. In this an efficient scheme for implementing a complex multiplier based on CORDIC arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic also proposed for computing. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which includes only three types of blocks, multiplexers, exclusive OR gates, and latches. The implementation is done using a robust differential single-phase clocked logic style suitable for high-speed and low power operation. The resulting application of the complex multiplier has a maximum clock frequency.

Volume 11 | 04-Special Issue

Pages: 1218-1221