Implementation of De-interleaver in WIMAX Using FPGA

K. Jeevitha, Prof. K. Manju and Prof. S. Vijayashaarathi

High speed architectures for finding the first two maximum/minimum values are of paramount importance in several applications, including iterative Encoders/decoders. It has a special feature to transfer the data in on-chip named as transitional encoder. Its operation is based on transitions of input data. The proposed system yields lower dynamic power dissipation due to the reduction of switching activity and coupling switching activity when compared to existing system. Even-though many factors which are based on power dissipation, the dynamic power dissipation is only considerable for reasonable advantage. Besides, the proposed system soft-decision FEC (SD-FEC) will be extended up-to interlink communication (data transfer from one to other) with help of routers and PEs which are performed by various operations. The processing step that it produces only two different output magnitude values irrespective of the number of incoming bit-to check messages. These new micro-architecture structures would employ the minimum number of comparators by exploiting the concept of survivors in the search. These would result in reduced number of comparisons and consequently reduced energy use. Reserving encoder /decoder are complex units and play an important role in deciding the overall area, speed and power consumption of digital designs. By using the multiplier we can reduce the parameters like latency, complexity and power consumption.

Volume 11 | 04-Special Issue

Pages: 1211-1217