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Low Power VLSI Design of TSPC D Flip-flop


S.Karunakaran, P.Tamilarasu, M.Sugumaran and P.N.Palanisamy
Abstract

Leakage of power and power consumption are the major challenges in CMOS technology. These constraints and the performance of a VLSI chip depends on the physical design of the chip. Its functionality is mainly controlled by the flip-flops. Since there are wide applications of flip-flops in Registers, Counters and Frequency divider circuits, an efficient designing of flip-flops is necessary to overcome the above said challenges.

Volume 12 | 08-Special Issue

Pages: 552-556

DOI: 10.5373/JARDCS/V12SP8/20202554