Pulsed latch came out as an standard sequence constituent for lowering power digital circuit, accommodating as an different of flip-flops. In this section we will be discussing about less Power n-bit pulsed latches which are projected to construct pipeline point in synchronous circuits. The process of integrating the projected n-bit size pulsed latches in the economic design flows is withal introduced. By using the n-bit pulsed latches nearly 45% potency savings can be accomplished for a class of Low Power Pulsed Generator designs Moreover, the potency utilization of the clock spreading network is reduced by83% and layout area is reduced 16% with the projected n-bit pulsed-latches as corelated to the flipflop predicated designs.
Volume 12 | Issue 6
Pages: 1503-1509
DOI: 10.5373/JARDCS/V12I2/S20201347