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CMOS implementation for Low Power Analog Multiplier


AnkitaTijare, PravinDakhole, RoshanUmate
Abstract

Anew CMOS voltage-mode Four-quadrant analog Multiplier is proposed and analyzed. By applying inputs signals to bulk of MOS transistor the circuit works in exponential manner. Based on the proposed multiplier circuit, a low voltage high performance CMOS four quadrant analog multiplier is designed and simulated by using 180nm technology. The measured 3dB bandwidth is 200.33MHz. Simple structure, low-voltage, low power, and high performance makes the proposed multiplier quite feasible in many applications.

Volume 11 | 08-Special Issue

Pages: 3006-3012