In this paper, Implementation of High speed and Low power digital circuits by adopting novel circuits of XOR and XNOR gates in order to optimize Delay, Power Consumption and Power Delay Product (PDP) parameters of the Digital circuits. The Optimization of PDP is also achieved by applying the transistor sizing method of Particle Swarm Optimization (PSO) Algorithm in order to reduce the size of the transistor to an optimized level. The Proposed novel circuits of XOR and XNOR functions are used to implement the digital circuit designs and their Performance parameters were analysed. The Performance of the circuit designs were analysed in Mentor Graphics tool. The Simulation results of the 130nm technology were compared with 65nm technology in terms of their Performance parameters such as Average Power, Delay, and PDP. The Search and Optimization process of Particle Swarm Optimization Algorithm is applied to attain the optimized value for PDP. The designed circuits are analysed in terms of various ranges of the Supply Voltages and the size of transistors.
Volume 12 | Issue 2
Pages: 1101-1108
DOI: 10.5373/JARDCS/V12I2/S20201141