Optimization of FIR Filter,Multirate Polyphase Decimator and Interpolator using MCM and Digit Serial Architecture

Dr. Rajendra ,M. Rewatkar1, Dr. Sanjay L. Badjate

Optimization technique of Multirate FIR filter,Multirate Polyphase Decimator and interpolatorusing different architecture is Proposed.The devicesare designed by digit serial ,MCM with shift add techniques so that circuit complexity will be reduced.Multiplier, adders and latches are reduced by different logic due to which power and area in the systemis reduced at greatextend. The primary objective is an optimization using Multirate DSP rather than targeting a single rate DSP, The proposed system approach can implement for the inprovement in the essential Parameters area,PowerDissipiation Speed and complexity. An approach provides the design and testing of the FIR filter,Multirate Polyphase decimator and Interpolator by using MCM and digit-serial architecture which offers alternative low complexity designs.MCM is an efficient way to reduce the number of addition and subtraction in FIR filter implementation. Experimental results have shown the efficiency of the proposed technique and the analysis of a different architectures. The simulation of parameters is analyzed by using Active HDL, Synopsis 45NM and Xilinx and verified on the FPGA platform.

Volume 11 | 02-Special Issue

Pages: 1268-1282