Implementation of Energy Efficient Adders using Advanced Power Optimization Techniques

T. Suguna,M.Janaki Rani,M. Anand

Adders are the basic building blocks used intermittently in microprocessors, digital signal processors and data processing ASICs. All types of other arithmetic operations can be performed only by using adders. In this paper adders like Half Adder, Full Adder, Carry Save Adder and Carry Skip Adder are implemented using conventional CMOS and GDI technique. This technique is used for implementation of a wide range of complex logic functions with high speed, reduced complexity, low power and area as prevalence characteristics. In the proposed work advanced power optimization techniques like multi- threshold CMOS (MTCMOS) and Low Power State Retention Technique [LPSR] are applied to the GDI adders to minimize the power. All the proposed adders are designed and simulated using DSCH and MICROWIND tool for 120nm technology. Power for all the proposed adders are compared at different supply voltages like 3.5V, 2.2V and 1V. It is observed that compare to conventional CMOS adders the proposed adders consume less power. For carry skip adder at 2.2V supply voltage 70% of power for MTCMOS technique and 65% of power for LFSR technique has been saved compared to the conventional CMOS Carry Skip Adder.

Volume 11 | 02-Special Issue

Pages: 745-756