Area Optimized Nano-Metric Level Dual Port Memory Design In Qca

A.Kamaraj, R.Abirami, Dr.P.Marichamy

Memory and its access play a key role in the design and performance of the Processor. In order to achieve high speed computing machine the memory access should also be equally faster. In this project, Dual port memory with Asynchronous/Synchronous Set/Reset is designed using Majority Voter (MV) in QCA. Dual port memory consists of basic fundamental blocks such as 2:4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Macro memory cell (MC), AND-OR block for write/read signal block and AND-OR block for Input/Output. These blocks are designed using the majority voter. Quantum-dot Cellular Automata (QCA) is one of the leading technologies in the electronics industry. The design of Dual Port Memory is validated using QCA. The area of the design is improved using the novel crossing scheme named as Logical Crossing. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is worth mentioning that approximately30%, 13%, 8%, 2% and 3%are percentage of improvement in number of cells in Decoder, ACB, CLB, Write/read signal and Memory Cell respectively. Also approximately, 57%, 49%, 68%, 93% and 90% of improvement in area for Decoder, ACB, CLB, Write/read signal and Memory Cell respectively. In addition the proposed logical crossing based Dual port memory achieves 77.23% of overall area and 5.5% of overall number of cells improvement.

Volume 11 | Issue 7

Pages: 739-748