Multipliers form a significant unit in all processor designs specifically for digital signal processors which involve ample mathematical operations including multiplication and division. Thus, Design optimization of a multiplier unit directly optimizes the processor design. It is difficult to take care of all three basic parameters of design optimization i.e. power, area and delay at the same time. In this paper, it is aimed to optimize all parameters. Considering delay and area, Vedic multipliers are fast and area efficient with respect to conventional multiplier architectures. These multipliers are proven to be a better choice for implementation of high performance complex FFT and DSP architectures. In this paper two new and modified 16 bit Vedic Multipliers based on Urdhwa Triyakbhyam (UT) are proposed. Since Adders are basic components of a multiplier design, here the proposed multipliers are implemented using modified carry select adder architectures (CSLA). Vedic Multiplier-1designed using novel CSLA based on Weinberger architecture occupies 2% lesser area and dissipates low power. On the other hand Vedic Multiplier 2 designed using modified Ling adder architecture is best in terms of performance with optimized power, area and delay. All adder architectures and proposed multipliers are simulated in Xilinx Vivado 14.4 tool and implemented on 28nmzynq7000FPGA board.
Volume 11 | Issue 10
Pages: 44-51
DOI: 10.5373/JARDCS/V11I10/20193004