A Multiplier Design based on Ancient Indian Vedic Mathematics Using Reversible Logic: A Review

S. Hridya, Dr.S. Bhavani, Dr.K.G. Dharani and M. Darani Kumar

Very Large-Scale Integration (VLSI) is a technique for creating a single chip by integrating thousands of transistors that are capable of performing various operation. The most important factor to consider in the VLSI design is Power dissipation, which is a critical challenge to create a low-power and high speed circuit. Multiplier has an important function in many processor and computational applications. The system’s performance mainly depends on the multiplier circuit; so, the main goal of designing a multiplier is to reduce delay and power dissipation. Improved Vedic multiplier architecture with reversible logic can decrease power dissipation and increase a system’s speed. Optical computing, quantum computing, Nanotechnology and low power design are some of the areas of application in Reversible logic gates. Here, a detailed investigation is performed to find that reversible Vedic multiplier is foremost in terms of area, power, delay, memory and quantum-cost compared to the conventional multiplier.

Volume 11 | 10-Special Issue

Pages: 911-924

DOI: 10.5373/JARDCS/V11SP10/20192887