Power Optimized Carry Select Adder Using Power Gated ALFA Cell

K. Murugan and S. Baulkani

In VLSI techniques power reduction plays important role which is achieved by power gating techniques. By reducing the leakage power, the total power consumption is also reduced. With the consideration of low power consumption, in this paper Carry Select Adder (CSA) is designed using Adiabatic Logic based Full Adder (ALFA) cell that exploits a hybrid power gating technique. It is mainly based on stacking effect that reduces the leakage power by turned off the number of transistors in a series manner. The proposed CSA illustrate output derived tanner tool 125nano meter technology. The proposed CSA module diminished power by 85.90%, 64.72%, 38.25%, 9.60% for 8 bit and 87.58%, 69.88%, 29.88%, 3.46% for 16 bit CSA when compared to CSA with Pass Transistor Logic based 16T FA, CSA Hybrid FA, CSA PTL 14T and CSA ALFA cell.

Volume 11 | 10-Special Issue

Pages: 821-826

DOI: 10.5373/JARDCS/V11SP10/20192878