Implementation of Novel Floating Point Adder for High Speed DSP Applications

Dr. R. Prakash Rao, B. Indira Priyadarshini, N.A.S. Keerthi, K. Praveen,

The major limitation of all the DSP processors is speed. But, now a days speed is the major concern for all the DSP applications along with the constraints of power consumption and area. The speed of operation of the DSP system depends on the DSP processor. The DSP processor is constituted by either IIR filters or FIR filters. These filters are constituted by MAC. MAC is constituted by multiplier, adder and shifter. In a MAC, adder adds any two numbers through the serial addition operation. In the first clock pulse addition of first number with the second number takes place. Then suppose to add 16 numbers it needs 16 clock pulses since serial addition operation. Instead of adding the numbers serially, if they are added in parallel and pipeline operation then speed of an adder can be improved. That intern the speed of MAC and IIR or FIR filters will be improved, consecutively DSP processor speed also will be improved.

Volume 11 | 05-Special Issue

Pages: 2368-2373