This paper describes a single precision and double precision IEEE 754 floating point format binary floating multiplier using modified Dadda algorithm. A 32 bit design is targeted to FPGA of Virtex6 xc6vlx240t- 1ff1156 device and virtex5 xc5vlx20t-2ff323 device. Both are compared with previously designed Dadda multiplier module. Proposed binary floating point multiplier achieves maximum frequency of 702.74 MHz with 597 slice area in virtex6 FPGA. This same design achieves the frequency of 610.873 MHz with 619 slices in Vertex5 FPGA family. Proposed design unit for 64 bit floating point multiplication achieves frequency of 549.74 MHz at the cost of 1982 slices. For reducing delays in the formation of the partial product matrix, left shifting technique is used instead of AND gates which results in decrease in slice utilization. The speed of multiplier is increased but numbers of LUT-flip flop pairs used are also increases in the design of double precision floating point multiplier.
Volume 11 | 08-Special Issue
Pages: 3199-3207