In this contemporary age, communication or data transmissionthat is executed in a wireless medium plays a significant part in a human’s life. For the transmission of secret data in the wire-less medium, cryptography techniques are vital that guards electronic data in a communication network. There are many cryptographically secure algorithms; however, they can't be effortlessly applied in computer applications particularly in hardware. Here, hardware effective hybrid wireless cryptoprocessor (HWCP) is proposed, which unites '2' block ciphers, i) enhanced advanced encryption standard (AES), ii) Sides-Channel Resistant Authenticated encryption with Masking (SCREAM). This utilizes composite field arithmetic (CFA), on the fly key expansion, and order change to lessen the hardware parts on the encryption algorithms. The proposed HWCP design augments security by increasing the cracking keys' complexity. Furthermore, the proposed HWCP is applied with a parallel sub-pipeline manner, which augments the throughput. The proposed HWCP synthesized with disparate FPGA kin is Virtex-6 (xc6vlx75t-2), Artix-7 (xc7a100t-2), Kintex-7 (xc7k70t-2), along with Virtex-7 (7vx330t-2) in Xilinx tool. The performance comparison of HWCP contrasted with prevailing designs regarding hardware use, power consumption, as well as the maximum operating frequency.
Volume 12 | 02-Special Issue
Pages: 992-1010
DOI: 10.5373/JARDCS/V12SP2/SP20201157