Full Adders are one amongst the fundamental logic circuits which are used widely in almost each and every computing device. Improvising the speed and reducing the power consumption of these Full Adder circuits will positively impact the current computational industry by virtue of its popularity. A 1-bit Full Adder circuit is proposed in this paper. The proposed design has been simulated by using 32 nm CNFET Technology at a supply voltage (VDD) of +0.9 V with the help of Cadence Virtuoso CAD tool. Parametric analysis of various full adder designs (as available in literature) along with the proposed designs has been undertaken in terms of power, delay and power-delay product (PDP). Further the proposed full adder circuit is used in designing applications like Carry Look-ahead adder (CLA) and Carry Increment Adder (CIA).
Volume 11 | 07-Special Issue
Pages: 161-168