Basically, Adders are one of the critical element in VLSI chips. Adders are used in every circuit such as ALUs, floating point arithmetic units, memory addressing and program counting. But here we are discussing about prefix adders, which are based on parallel prefix circuit theory by providing a solid theoretical basis for wide range of design trade-offs between delay, area and wiring complexity. Basically, Parallel prefix circuits are performing the prefix operation for the computational circuit model. Here the size of prefix circuit is depend on the number of operation nodes in the circuit, and the depth depends on the maximum level of operation nodes. In this paper, we present a new approach that is propagator and generator to easing the design of parallel prefix adder. Here a vlsi synthesis tool is used to generate parallel prefix carry trees with variable parameters like carry tree width, prefix cell valence, and the spacing of repeated carry trees. Hence the proposed system produces low logical depths and it also reduces the end around carry adders fan out readings compared to ripple carry adder and carry look ahead adder.
Volume 11 | Issue 1